pub fn w8a16_gemv_batch16_strided(
gpu: &dyn GpuBackend,
kernel: KernelHandle,
input: DevicePtr,
weight: DevicePtr,
block_scale: DevicePtr,
output: DevicePtr,
m: u32,
n: u32,
k: u32,
a_row_stride: u32,
c_row_stride: u32,
stream: u64,
) -> Result<()>Expand description
MAX_M=16 sibling of w8a16_gemv_batch4_strided, for decode concurrency
5..=16. Same template, same launch geometry, same per-row accumulation
order; the wider register array is the only difference.
Kernel: w8a16_gemv_batch16_strided (module w8a16_gemv_batch4).
Grid: (ceil(N/4), 1, 1) Block: (256, 1, 1)